In the electronics industry, the tendency has been to reduce the size of electronic devices such as camcorders and portable telephones while increasing performance and speed. Integrated circuit packages for complex systems typically are comprised of a multiplicity of interconnected integrated circuit chips. The integrated circuit chips usually are made from a semiconductor material such as silicon or gallium arsenide. Semiconductor devices are formed in the various layers of the integrated circuit chips using photolithographic techniques. The integrated circuit chips may be mounted in packages that are then mounted on printed wiring boards.
Packages including integrated circuit chips typically have numerous external pins that are mechanically attached by solder or a variety of other known techniques to conductor patterns on the printed wiring board.
Typically, the packages on which these integrated semiconductor chips are mounted include a substrate or other chip mounting device. One example of such a substrate is a leadframe. High performance leadframes typically are multi-layer structures including power, ground, and signal planes.
Leadframes also typically include at least an area on which an integrated circuit chip is mounted and a plurality of power, ground, and/or signal leads to which power, ground, and/or signal sites of the integrated semiconductor chip are electronically attached. Semiconductor integrated chips may be attached to the leadframe using adhesive or any other techniques for attaching such chips to a leadframe which are commonly known to those skilled in the art, such as soldering. The power, ground and signal sites on the chip may then be electrically connected to selected power, ground and signal plane or individual leads of the leadframe.
Leadframes have been used extensively in the integrated circuit packaging industry mainly because of their low manufacturing cost and high reliability. Leadframe packages remain a cost-effective solution for packaging integrated circuits despite the introduction of various leadless packages in recent years.
Typical leadframe packages include a die attach paddle, or pad, surrounded by a number of leads. The leads are temporarily attached to the die attach paddle. An integrated circuit chip, is attached to the die attach paddle using a conductive adhesive such as silver epoxy. The conductive adhesive is cured after die attach. After the die is attached to the die paddle, a wire-bonding process is used to make electrical interconnections between the integrated circuit and the leads of the leadframe. After wire bonding, the leadframe with the integrated circuit attached is encapsulated using a molding compound.
Such enclosures may include encapsulation in a plastic or a multi-part housing made of plastic ceramic, or metal. The enclosure protects the leadframe and the attached chip from physical, electrical, and/or chemical damage. Finally, post mold curing and singulation steps are conducted to complete the packaging process.
The leadframe and attached chip(s) may then be mounted on, for example, a circuit board, or card along with other leadframes or devices. The circuit board or card may then be incorporated into a wide variety of devices such as computers, automobiles, and appliances, among others.
As integrated circuits have become smaller with increased performance capabilities leadframes for integrated circuits have been adapted to accommodate these integrated circuits. A staggered dual row leadframe has found increased use to provide additional leads on a leadframe of a given size. The dual row leadframe includes an inner row of leads and an outer row of leads surrounding a pad to which the integrated circuit die is attached. The contact pads on the integrated circuit are connected to the inner and the outer rows of leads with bonding wires in accordance with the particular design of the semiconductor package.
One problem that persists with dual row leadframes is that the length of the bonding wires to the inner row of leads is shorter than the length of the bonding wires to the outer row of leads. The length of the bonding wires can effect the electrical performance of the semiconductor package. Connections that are considered critical to the operation of the semiconductor package usually need to be positioned to use the shorter bonding wire length to improve the performance of the semiconductor package thus restricting flexibility in the design of the integrated circuit.
Additionally, dual row leadframes have a tie bar located at the corners of the leadframe to temporarily attach the leads to the die attach paddle. During encapsulation and singulation of the dies, the corner tie bar can be dislocated from the mold creating a path for moisture or other contaminants to contact the integrated circuit thereby causing failures of the semiconductor packages.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.